Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications

Mathematical analysis and empirical evaluation of the solid state equation PowerCMOS = P = C ⋅V2 ⋅ f ⋅ N ⋅%N is presented in this paper which identifies a measurable metric for evaluating relative advantages of ASIC, DSP, and RISC architectures for embedded applications. Relationships are examined which can help predict relative future architecture performance as new generations of CMOS solid state technology become available. In particular, Performance/Watt is shown to be an Architecture-Technology Metric which can be used to • calibrate ASIC, DSP, & RISC performance density potential relative to a solid state technology generations, • measure & evaluate architectural changes, and • project a architecture performance density roadmap. 1. Architecture Metric Basis Intuitively, more efficient architectures will use less energy to complete the same task on the same generation CMOS solid state technology. Beyond this intuition, (1) How can the relative advantages between ASIC, DSP, and RISC architectures be quantified? (2) How can the relative advantages between different ASIC, DSP, and RISC options be projected into future embedded system design plans? The key concept is the power consumption behavior of a CMOS gate. 1.1. CMOS device power consumption Power consumption is an externally measurable physical property of CMOS ASIC, DSP, and RISC devices which are used to build larger computational systems. The power consumption for a CMOS device is shown in equation 1-1. PowerCPU = P = C ⋅V 2 ⋅ f ⋅ N ⋅%N ( 1 -1 ) where, C = Capacitance V = CPU Core Voltage f = CPU Core Clock Frequency N = Number of Gates %N = Percentage of Gates which change state on a given clock cycle. Some primary architectural and technoloyg components in the CMOS power consumption equation 1-1 can be noted.